Pcb

Enric Herrero Abellanas

Research

IBM Power5

Computer Architecture

Nowadays I'm a PhD student of the ARCO Research Group (UPC and Intel Barcelona Research Center). I am working in the optimization of the microarchitecture of multicore architectures. And more specifically in the improvement of performance and power consumption of the memory hierarchy. My advisors are Ramon Canal and José González.

During fall quarter 2009 I worked with Professor Dean Tullsen at the University of California in San Diego (UCSD)

Publications

Conferences

E. Herrero, J. González i R. Canal. Elastic Cooperative Caching: An Autonomous Dynamically Adaptive Memory Hierarchy for Chip Multiprocessors. In the 37th International Symposium on Computer Architecture (ISCA'10), June 2010.

E. Herrero, J. González and R. Canal. Distributed Cooperative Caching. In the 17th International Conference on Parallel Architectures and Compilation Techniques (PACT'08), October 2008.

E. Herrero, J. González and R. Canal. A scalable and power efficient memory hierarchy. In the Intel European Research and Innovation Conference, September 2008. (Poster).

Technical Reports

E. Herrero, J. González and R. Canal. Architectural Level Power Simulator of the Memory Hierarchy of Chip Multiprocessors. UPC Technical Report UPC-DAC-RR-ARCO-2008-3, June 2008.

E. Herrero, M.A. Tirado and M. Brorsson. Scalability of a Directory Cache based Memory Management Protocol in Mesh CMPs. KTH Technical Report ICT/ECS-2006-100, August 2006.

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